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DFT Technical Manager/Lead |
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Summary: Lead test methodology development and implementation of test chips in advanced process nodes Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation Verify DFT circuitry and interface with other blocks, debug timing simulation issues Closely work with physical design team to generate and validate timing constraints Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning Be able to work independently and own the complete task from DFT specification ... Category: Manager | |
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